Memory circuits are commonly manufactured using thousands of transistors to store data. Each of the transistors has a gate or control electrode and two current electrodes known as a source and a drain in metal oxide semiconductor (MOS) technology. The source and the drain typically reside in a well region formed in a substrate. The source and drain are adjacent to the gate which is commonly elevated above the source and drain. For NVM transistors, a storage layer is placed between the gate and an underlying body that separates the source and the drain. The body is characterized as having an upper portion that is depleted of either holes or electrons depending upon the conductivity type of the transistor. Unless a transistor is a fully depleted device, a portion of the body is not depleted. The storage layer may store either electrons or holes that modulate the threshold voltage of the memory device. The threshold voltage is the voltage at which the transistor begins to conduct electrons (NMOS) or holes (PMOS). Several methods exist in which electrons or holes may be placed onto the storage layer. For example, a technique known as “hot carrier injection” or HCI occurs when a high gate and a high drain bias is applied relative to the source. For NMOS, electrons go from the source to the drain. A high electric field exists at the drain as a result. The high electric field creates impact ionization which injects electrons to the storage layer and holes are created near and in the drain region.
The term “bulk device” is commonly used to refer to a transistor having a well region in which the source, drain and channel reside. A connection to the well region is used to bias the well region. In bulk devices, the holes that are being created form a current that comes out through the well electrode. However, in SOI in which a floating body exists there is no well contact and thus the holes build up in the body until they eventually recombine with electrons at the source, drain or body. For bulk NVM devices, the junctions typically have low mid-bandgap defect densities. As a result, if the same junction structures are used in SOI, the recombination time is very long compared to the operations (e.g. programming, reading, erasing, etc.) of the nonvolatile memory device. As used herein, recombination time refers to the time required for holes and electrons to be neutralized in charge. The long recombination time thus makes the threshold voltage of the memory device vary over time.
Another problem is that during the programming operation the holes may build up to such an extent that they do not allow the programming operation to function completely or to fail. This occurs due to two effects. A first effect is the reduction of the lateral electric field between the drain and the body of the NVM transistor cell. As the holes build up, the lateral electric field is reduced when the body potential rises while the drain potential is fixed. A second effect is the reduction of the vertical electric field between a storage medium and the body. As the holes build up, the vertical electric field is reduced when the body potential rises while the control gate potential is fixed.
Yet another problem for transistors with a floating body is that as the floating body bias becomes high, an inherent bipolar transistor inherent in any MOS transistor becomes conductive. The biasing of the inherent transistor may result in avalanche breakdown at the drain of the floating body device. A common symptom of this phenomena is ruptured gate oxides and thermal damage to the drain junction which permanently modifies desired electrical characteristics. These issues limit the usefulness of implementing NVM cells on SOI.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.